1. Field of the Invention
The invention relates to testing of devices, and more particularly to measuring delay periods of tested devices.
2. Description of the Related Art
When an electronic device receives an input signal, the electronic device requires a time period to generate an output signal in response to the input signal. The time period is referred to as a delay period of the electronic device. A delay period of an electronic device reflects performance of the electronic device. Generally, a high-performance electronic device has a short delay period, and a low-performance electronic device has a long delay period.
When a system comprises a plurality of cascaded electronic devices, the total delay period of the system is a sum of the delay periods of all the cascaded electronic devices. Thus, to assure acceptable performance of the system, normally, the total delay period of the system is limited to be shorter than a threshold level. A delay period of an electronic device is therefore an important factor in evaluating performance of a system comprising the electronic device.
A logic tester is conventionally used to measure a delay period of an electronic device. Referring to FIG. 1, a block diagram of a testing system 100 comprising a conventional logic tester 102 is shown. In one embodiment, the logic tester 102 comprises a function generator 104 and a time counter 106. In addition to the logic tester 102, the system 100 further comprises a plurality of switches 122˜12N and 132˜13N, and a plurality of tested devices 112, 114, . . . , 11N. An output terminal SI of the logic tester 102 is coupled to input terminals SI1, SI2, . . . , SIN of the tested devices 112, 114, . . . , 11N via the switches 122˜12N. Similarly, an input terminal SO of the logic tester 102 is coupled to output terminals SO1, SO2, . . . , SON of the tested devices 112, 114, . . . , 11N via the switches 132˜13N. Because the logic tester 102 cannot simultaneously measure delay periods of two tested devices, the logic tester must respectively measures the delay periods of the tested devices 112˜11N one by one.
Referring to FIG. 2, a flowchart of a method 200 for measuring delay periods of tested devices is shown. The logic tester 102 operates according to the method 200 to measure delay periods of the tested devices 112˜11N. First, an operator of the testing system 100 selects a target tested device from the tested devices 112, 114, . . . , 11N (step 202). Assume that the target tested device is the tested device 112. The operator therefore switches on the switches 122 and 132 to couple the tested device 112 to the logic tester 102, and switches off the other switches 124˜12N and 134˜13N. The logic tester 102 then generates an initial code sequence as an input signal of the target tested device 112 (step 204). In one embodiment, the function generator 104 generates the initial code sequence. When the target tested device 112 receives the initial code sequence, the target tested device 112 fixes an output signal SO1 thereof to a first value.
The logic tester 102 then generates a functional code sequence as an input signal of the target tested device 112 (step 206). In one embodiment, the function generator 104 generates the functional code sequence. After the functional code sequence is generated, the output signal SO1 of the target tested device 112 changes from the first value to a second value. When the functional code sequence is generated (step 208), the logic tester 102 monitors the output signal SO1 of the target tested device 112 (step 210), and a time counter 106 of the logic tester 102 starts to accumulate a delay period of the target tested device 112 (step 212).
When the logic tester 102 detects that the value of the output signal SO1 of the target tested device 112 changes from the first value to a second value (step 214), the time counter 106 stops accumulation of the delay period, and outputs the delay period (step 216). Testing of the target tested device 112 is therefore completed. If there are still tested devices which have not been tested (step 218), the operator selects a new target tested device from the tested devices 114˜11N (step 202), switches on the switches corresponding to the new target tested device, and switches off the switches corresponding to other tested devices. The logic tester 102 then executes steps 204˜216 again to measure the delay period of the new tested device. The testing process is continued until all of the tested devices 112˜11N in the testing system 100 have been tested.
Because the logic tester 102 can only measure a delay period of a tested device one at a time, when there are many tested devices in the testing system 100, the logic tester 102 has to repeat the steps 204˜218 for many times, requiring much time to be spent and effort of the operator of the testing system 100. In addition, when the target tested device is changed, the operator has to decouple the old target tested device from the logic tester 102 and couple the new target tested device to the logic tester 102. The conventional logic tester 102 shown in FIG. 1 is therefore inconvenient for the operator of the testing system 100. A logic tester capable of simultaneously measuring delay periods of multiple tested devices is therefore required.